This invention pertains to three dimensional integrated circuits and apparatuses, methods, and systems for fabricating three-dimensional integrated circuits; more specifically this invention relates to apparatuses, methods, and systems for interconnect metallization of three-dimensional integrated circuits.
A three-dimensional integrated circuit includes two or more semiconductor chips with integrated circuits or includes two or more semiconductor wafers with integrated circuits. The semiconductor chips or semiconductor wafers are stacked together, bonded, and electrically interconnected in three dimensions, i.e., integrated within the semiconductor chips or semiconductor wafers and integrated between the semiconductor chips or semiconductor wafers. The interconnections between the chips or between the wafers are accomplished by way of through holes from the back side to the front side of one or more of the chips or one or more of the semiconductor wafers. In other words, the electrical connections between the stack of chips or stack of wafers are made by way of the through holes. Three-dimensional integrated circuits have a large number of through holes for interconnect metallization between the semiconductor chips or between the semiconductor wafers.
Three-dimensional integrated circuits, according to some designs, will use through holes having diameters of less than 1 micrometer. The length for some of the through holes will be in the range of a few micrometers to 20 or more micrometers. Consequently, the aspect ratios for processing the through holes are extremely high in comparison to standard technologies for fabricating two-dimensional integrated circuits. Typical processes for fabricating two-dimensional integrated circuits cannot easily handle the extremely high aspect ratios that will be required for fabricating three-dimensional integrated circuits. Also, typical processes for fabricating two-dimensional integrated circuits are designed for processing blind holes. Additional process steps are needed to form the through holes successfully.
For the specific example of copper metallization, the requirements for three-dimensional integrated circuits may include deposition of a dielectric layer on the sidewalls of the through hole, deposition of a barrier layer on the dielectric layer, and a copper fill sufficient to allow electrical interconnection of circuits on different chips or wafers in the stack. These requirements coupled with the extreme aspect ratios for three-dimensional integrated circuits make the prospects for successful fabrication of three-dimensional integrated circuits using standard two-dimensional integrated circuit processing technology extremely poor.
Clearly, all of the requirements for fabricating three-dimensional integrated circuits cannot be met using standard two-dimensional integrated circuit fabrication technology. The practical fabrication of three-dimensional integrated circuits will require new processes, apparatuses, and systems capable of meeting the requirements for metallization of three-dimensional integrated circuits. More specifically, there is a need for new processes, apparatuses, and systems capable of meeting the extreme aspect ratio requirements for three-dimensional integrated circuits while providing deposits of materials such as insulators, barrier layers, and metals sufficient in quality for high-performance devices.